Dynomotion

Group: DynoMotion Message: 6293 From: azubar@ymail.com Date: 12/17/2012
Subject: I/O signal specs
I'm going to build an isolator board for my stepper system to JP7 and maybe JP4. Are these electricsl specs published for these signals so I can design the opto board?

What are the Vih and Vil Iih and Iil Voh, Vol, Ioh, Iol specs for the inputs and outputs?

The pulse direction signal outputs can be set up as open collector or pushpull. What are the voltage / current specs for these options?
My stepper requires a minimum of 10 ma and a max of 20 ma to drive the step direction inputs. Will the open collector be able to drive that directly assuming the 5 volt supply and 1.75 volts drop across the input opto diode of the stepper?

Are the inputs on JP7 and others active hi or active lo?
Are the outputs on JP7 and others active hi or active lo (open coll)
Do they have internal pullups or pull downs and what value are they?

Thanks,
Alex
Group: DynoMotion Message: 6294 From: Tom Kerekes Date: 12/17/2012
Subject: Re: I/O signal specs
Hi Alex,

The 46 KFLOP IO are all basically LVTTL compatable from a Xilinx FPGA.  The Xilinx Data Sheet is here:

http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf
See DC Switching Characteristics | Single Ended IO | LVTTL

All IO set to source/sink 16ma

All IO is set to "slow" (slow to the FPGA is ~ 1ns)

16 IO have 150ohm pull down resistors (first 8 on JP4 and JP6)

24 have 47 ohm series resistors to make them +5V tolerant (first 16 on JP7 and 8 on JP5)  (although driving above 3.8V is not recommended).

All remaining are straight LVTTL

All IO are diode clamped to the 3.3V power (and GND rails) in the FPGA.

As inputs they are MOSFET and so take virtually zero current (megohms) but have some capacitance.

All inputs and outputs can be configured as active high or low in software.

HTH
Regards
TK